As is known to those in the semiconductor art, interconnect delay is a major limiting factor in the drive to improve the speed and performance of integrated circuits (IC). One way to minimize interconnect delay is to reduce interconnect capacitance by using low dielectric constant (low-k) materials during production of the IC. Thus, in recent years, low-k materials have been developed to replace relatively high dielectric constant insulating materials, such as silicon dioxide. In particular, low-k films are being utilized for inter-level and intra-level dielectric layers between metal layers of semiconductor devices. Additionally, in order to further reduce the dielectric constant of insulating materials, material films are formed with pores, i.e., porous low-k dielectric films. Such low-k films can be deposited by a spin-on dielectric (SOD) method similar to the application of photo-resist, or by chemical vapor deposition (CVD). Thus, the use of low-k materials is readily adaptable to existing semiconductor manufacturing processes. While low-k materials are promising for fabrication of semiconductor circuits, the present inventors have recognized that these films also provide many challenges. First, low-k films tend to be less robust than more traditional dielectric layers and can be damaged during wafer processing, such as by etch and plasma ashing processes generally used in patterning the dielectric layer. Further, some low-k films tend to be highly reactive when damaged, particularly after patterning, thereby allowing the low-k material to absorb water and/or react with other vapors and/or process contaminants that can alter the electrical properties of the dielectric layer. As a result, the low-k material, originally having a low dielectric constant, suffers damage leading to an increase in its dielectric constant and a loss of its initially intended benefit. At present, the removal of post-etch residue from advanced semiconductor devices having low-k layers has been facilitated by the exposure of these layers to a dry plasma ashing process. In particular, the dry plasma utilizes an oxygen-based chemistry; however, it has been observed that conventional oxygen plasma damages the low-k layer as described above. As an alternative, nitrogen, hydrogen and ammonia-based chemistries have been investigated, but these chemistries have demonstrated poor etch selectivity to the etch stop layer underlying the low-k layer. The removal of the etch stop layer during plasma ashing can lead to potential semiconductor device damage.